PI7C8150B Datasheet, Pericom Semiconductor Corporation

section in the introduction Revised register description bits[31:24] offset 18h - Secondary Latency Timer Register (section 14.1.13) Revised register description for bits.

First Release of Data Sheet Correction to description for bit[0] at offset 48h. Changed from Memory Read Flow Through Disable to Memory Read Flow Through Enable. Added reset condition to offset 4Ch, bits [31:28] Revised descriptions and added ordering information for PI7C8150B-33 (33MHz) device 06/.